1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory that has a memory cell with one floating gate and one select transistor as a basic circuit. More specifically, it relates to a nonvolatile semiconductor memory having a circuit structure that improves read-out speed.
2. Description of the Related Art
An electrically erasable programmable read-only memory (EEPROM), which performs data write-in and erase, has been known as a nonvolatile semiconductor memory (R. Shirota, ‘A Review of 256-Mbit NAND Flash Memories and NAND Flash Future Trend’, Non-Volatile Semiconductor Memory Workshop (NVSMW) 2000, p. 22–31.). In an EEPROM, especially a NAND type, a memory cell array is configured by deploying or positioning memory cells at the respective intersections of horizontal word lines and vertical bit lines. A MOS transistor having a stacked gate structure configured by stacking a floating gate and a control gate, for example, is typically used as a memory cell.
A representative memory cell of a NAND flash memory is described, for example, in R. Shirota, ‘A Review of 256-Mbit NAND Flash Memories and NAND Flash Future Trend’, Non-Volatile Semiconductor Memory Workshop (NVSMW) 2000, p. 22–31. The NAND flash memory is structured such that a plurality of memory cell transistors connected in series form a NAND string; and select transistors are deployed or positioning on both sides of that NAND string. In addition, device isolation regions are aligned in parallel to the device activation regions of the memory cells to form a memory cell array. Generally, the gate length of the select transistor is longer than that of the memory cell transistor to effectively prevent degradation in the cut-off characteristics of the transistor due to a short-channel effect. In addition, the select transistor is normally configured with an enhancement MOS transistor.
In the nonvolatile semiconductor memory with a memory cell configured with two transistors, such as a memory transistor and a select transistor, a structure thereof where the thicknesses of a gate oxide film for a memory transistor area and a gate oxide film for a selection transistor area are different from each other has been disclosed (Japanese Patent Application Laid-Open No. 2000-269361).
In addition, a structure where the film thicknesses of a gate oxide film of a selective MOS transistor formed by a gate electrode and a gate oxide film of a MOS transistor in a peripheral circuit are different from each other, has been disclosed (Japanese Patent Application Laid-Open No. Hei 04-165670).